The invention is in the field of semiconductor technology and is directed to a semiconductor memory cell
having a layer structure that comprises at least two semiconductor layers with a dielectric lying therebetween and at least one control electrode for controlling a current flow through the layer structure, whereby the control electrode is arranged at an end face of the layer structure formed by the semiconductor layers and the dielectric upon interposition of an insulating layer and is connected to a word line;
having a bit line (BL);
and having a storage transistor, whereby the layer structure connects the bit line with the gate electrode of the storage transistor.
Prior and higher demands are being made of the functionability of semiconductor components with increasing miniaturization and integration density. Given, for example, semiconductor components that become smaller and smaller, it becomes increasingly more difficult to dependably suppress leakage currents. In what are referred to as PLEDs (planar localized electron devices), the problem of the leakage currents is to be alleviated by tunnel barriers in the channel region. The structure and the functioning of a PLED is described, for example, in the technical article by Nakazato et al, IEDM 97, pages 179-182, as well as in the previously published conference paper by Nakazato et al, xe2x80x9cPhase-state Low Electron-number Drive Random Access Memory (PLEDM)xe2x80x9d, ISSCC 2000, Feb. 8, 2000, Paper TA 7.4.
The structure of a PLED can be briefly summarized in the following way. The xe2x80x9cchannel regionxe2x80x9d of the PLED is formed by a layer structure of what are generally intrinsic semiconductor layers separated from one another by tunnel barriers, the layer structure being arranged between a source zone and a drain zone. A gate or control electrode that is insulated from the semiconductor layers is seated at an end face of the semiconductor layers. Given a voltage difference that is built up between source zone and drain zone, a flow of current is prevented on the basis of the potential walls formed by the tunnel barriers. The probability of a tunnel current is practically zero. Given a suitably selected gate voltage, the curve of the potential of the potential walls is lowered, so that the probability of a tunnel current through the tunnel barriers increases. A measurable tunnel current flows.
The functioning of the PLED can also be described by the course of the energy bands. In the off condition, the band spacing between conduction band and the Fermi edge is generally extremely high. This distance can be reduced by a modification of the gate voltage or can even be increased further. Given an adequately reduced distance, charge carriers can proceed with increased probability from the valence band into the conduction band (for example, due to thermal excitation). As a result thereof, charge carriers are available for a current flow.
Compared to a MOSFET, the PLED, on the one hand, in fact exhibits a low current yield; on the other hand, however, it exhibits an extremely high blocking effect with disappearing leakage current. The semiconductor memory cells disclosed in the prior art, for example in EP 0 843 360 A1, EP 0 901 169 A1 and EP 0 908 954 A2 require at least four interconnected lines, even five interconnected lines in some cases, for their drive. This increases the process expense for manufacturing such semiconductor memory cells. Moreover, the drive is complicated. Over and above this, the coupling ratio between word line and gate of the storage transistor is relatively slight in the prior art, so that the functioning of the known semiconductor memory cells is deteriorated.
It is an object of the invention to specify a semiconductor memory cell having an improved drive given a comparatively simple structure.
This object is achieved in that the semiconductor memory also comprises a selection transistor lying in series with the storage transistor, the gate electrode thereof being connected to the control electrode of the layer structure and to the word line, whereby the selection transistor and the storage transistor are arranged between the bit line and a ground line.
The invention is also based on an object of specifying a method for manufacturing a semiconductor memory cell. This object is achieved by a method for manufacturing a semiconductor memory cell having the steps of:
forming a layer sequence on a substrate, said layer sequence comprising at least two semiconductor layers with a dielectric lying therebetween;
etching the layer sequence upon employment of at least one mask down to the substrate, so that individual layer structures remain on the substrate;
forming insulation layers at at least one lateral surface of each layer structure as well as on the uncovered substrate and a word line proceeding thereat along the lateral surface of the layer structures is formed, said word line at least partially covering the insulation layer formed on the substrate;
forming doping regions laterally from the layer structures and the word line;
applying an insulating layer surface-wide; and
forming a via opening through the insulating layer to one of the doping regions.
An exemplary embodiment is shown in the Figures below.